The present invention relates to a system for transferring data between storage areas and, more particularly, to a data transfer system in which pointers to "free" buffers are allocated repetitively to transfer protocol data units from one data storage area into contiguous address spaces in another data storage area in a data communication switch.
Data communication switches receive packets from one network and switch them to other networks. Packets must be stored in data storage areas within such switches while switching information is processed and to avoid contention among packets competing for switching resources. Such transfers are often accomplished in hard-wired logic using direct memory access (DMA) transfer.
Basically, DMA transfer describes a process in which packets are transferred directly between a source and destination area of data storage instead of transferring them to a central processing unit and then from the central processing unit to the destination data storage area. By reducing the data transfer process to a relatively low-level task implemented in hard-wired logic, DMA transfer can often be accomplished faster than in processor-dependent data transfer. At the same time, however, DMA transfer's reliance on hard-wired logic as the transfer mechanism places practical constraints on how such transfers are effectuated. One constraint inherent in many DMA transfer systems requires that each packet be transferred into a contiguous address space within the destination area of data storage.
A technical challenge arising in DMA transfer systems requiring contiguity is how to buffer packets efficiently. In many conventional DMA transfer systems where there is no contiguity requirement, efficiency is achieved by allocating to packets pointers which address available, or "free", constant-byte buffers in a destination storage area in a repetitive cycle on an "as needed" basis. This results in relatively small packets being allocated a single buffer pointer and relatively large packets being allocated multiple buffer pointers. Because every packet is allocated the approximate amount of address space it needs, the destination storage area may be provided using a relatively small memory. Unfortunately, however, such efficient conventional systems fail to provide contiguity for multi-buffer packets because buffer pointers are inevitably returned and real-located in a different order than the order of original allocation. While it would be possible to guarantee contiguous address space by modifying such conventional systems such that every packet is allocated a single pointer to a buffer having a "system maximum" buffer size, i.e., a buffer size as large as the largest packet which might occur system-wide, smaller packets would then be allocated far more address space than they need and a relatively large memory would be required for the destination storage area. Thus, such a modified system would sacrifice efficiency for the sake of maintaining contiguity.
The above-stated problem often arises in multi-protocol switching environments. In such environments, the "system maximum" buffer size would be dictated by the protocol-specific packet size limitation which is the highest among all such limitations for the various protocols operative within the system. Selecting such a "system maximum" buffer size as a universal buffer size for the sake of maintaining contiguity would result in most packets being allocated substantially more address space in the destination data storage area than is actually required. Such an over-allocation of address space would create memory requirements for the destination storage area which are unacceptably high.
Accordingly, there is a general need for a DMA transfer system which allocates contiguous address spaces in the destination storage area that are not grossly oversized relative to the size of the buffered packets, and there is a particular need for a such a DMA transfer system in multi-protocol switching environments.